`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [1:0]cout_r;
reg [7:0]out_r;
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		cout_r<=2'b00;
		input_grant<=1'b0;
		out<=11'd0;
	end
	else begin
		if(cout_r==2'b00)begin
			cout_r<=2'b01;
			input_grant<=1'b1;
			out<={3'b000,d};
			out_r<=d;
		end
		else if(cout_r==2'b01)begin
			cout_r<=2'b10;
			input_grant<=1'b0;
			out<={2'b00,out_r,1'b0}+{3'b000,out_r};
			out_r<=out_r;
		end
		else if(cout_r==2'b10)begin
			cout_r<=2'b11;
			input_grant<=1'b0;
			out<={1'b0,out_r,2'b00}+out;
			out_r<=out_r;
		end
		else begin
			cout_r<=2'b00;
			input_grant<=1'b0;
			out<=out+out_r;
			out_r<=out_r;
		end
	end
end
//*************code***********//
endmodule